`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);
wire [3:0]y2;
wire [3:0]y1;
wire [3:0]y0;
comparator_2 comparator_2_1(A[3],B[3],y2[3],y1[3],y0[3]);
comparator_2 comparator_2_2(A[2],B[2],y2[2],y1[2],y0[2]);
comparator_2 comparator_2_3(A[1],B[1],y2[1],y1[1],y0[1]);
comparator_2 comparator_2_4(A[0],B[0],y2[0],y1[0],y0[0]);
    assign Y2=y2[3]|(y1[3]&y2[2])|(y1[3]&y1[2]&y2[1])|(y1[3]&y1[2]&y1[1]&y2[0]);
    assign Y1=y1[3]&y1[2]&y1[1]&y1[0];
    assign Y0=y0[3]|(y1[3]&y0[2])|(y1[3]&y1[2]&y0[1])|(y1[3]&y1[2]&y1[1]&y0[0]);

endmodule

module comparator_2(
	input a,
	input b,
	output y2,
	output y1,
	output y0
);
    assign y2=a&(!b);
    assign y1=(a&b)|(~a&~b);
    assign y0=(~a)&b;
    
endmodule